1. Field of the Invention
This disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a dual gate dielectric layer to improve a performance of semiconductor device.
2. Detailed Description of the Related Art
In general, a semiconductor technology related to a structure of a dual gate oxide layer is being variously applied to a semiconductor device such as DRAM. An increasing degree of integration for the semiconductor device increasingly requires miniaturization of the transistor. This also inevitably requires a technology that can provide gate insulation layers having mutually different thicknesses, for transistors formed on a cell array region to directly read and write data, and on a peripheral circuit region of the semiconductor device to operate the transistor of the cell array region. The gate insulation layer of the cell array region, where a relatively high voltage is applied, should be formed thicker than on the peripheral circuit region. In order to fabricate the varying thicknesses, a general photolithography process is employed to form the gate insulation layer.
For example, a first silicon oxide layer having a predetermined thickness is formed by a thermal oxidation process on a semiconductor substrate that is defined as a cell array region and a peripheral circuit region by a device isolation film, afterwhich a photoresist is deposited thereon. The first silicon oxide layer has a low dielectric constant of about 3.9.
Next, the photoresist is patterned to expose the first silicon oxide layer provided on the peripheral circuit region through a photolithography process. Then, the first silicon oxide layer formed on the peripheral circuit region is etched by using the photoresist as an etch mask, and the photoresist pattern is removed. Herewith, the etching process on the first silicon oxide layer is performed through a wet etching since a dry etching may damage a surface of the semiconductor substrate.
Lastly, a second silicon oxide layer is formed on the semiconductor substrate on which the first silicon oxide layer is formed. The silicon oxide layer is formed with a mutually different thickness on the cell region and the peripheral circuit region, thereby completing a formation process of the dual gate oxide layer.
Then, a gate electrode is formed on the semiconductor substrate on which the second silicon oxide layer is formed, and a gate protective layer is formed on the gate electrode. Also the gate electrode and the protective layer provided on a source/drain region are removed to form a gate stack on a gate region. A spacer is formed in a sidewall of the gate stack, and a source/drain electrode is formed on both sides of the gate stack so as to form a transistor.
Thus, in the method of forming the dual gate oxide layer according to the prior art, the silicon oxide layer can be formed with mutually different thicknesses on the cell region and the peripheral circuit region through the photolithography process.
However, the dual gate oxide layer forming method based on the prior art causes the following defects.
According to the prior art, the method of forming the dual gate oxide layer is provided to form a gate insulation layer by using a dielectric insulation layer (hereinafter, referred to as “a dielectric layer”) that has a dielectric constant higher than those of the first and second silicon oxide layers, but a wet etching process for a partial removal thereof after the formation of the dielectric layer is unstable, thus it is difficult to apply.